Distributed synchronization and timing system

ABSTRACT

A method and apparatus for controlling the phase and frequency of the local clock of a USB device, the apparatus comprising circuitry for observing USB traffic and decoding from the USB traffic a periodic data structure containing information about the frequency and phase of a distributed clock frequency, and phase and circuitry for receiving the periodic data structure and generating from at least the periodic data structure a local clock signal locked in both frequency and phase to the periodic data structure. The circuitry for receiving the periodic data structure and generating the local clock signal can generate the local clock signal with a frequency that is a non-integral multiple of a frequency of the periodic data structure.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.12/279,328, filed Jan. 21, 2009, which is a national stage entry ofInternational Application No. PCT/AU2007/000155, filed Feb. 15, 2007,which is based on and claims the benefit of the filing date of U.S.Provisional Application No. 60/773,537, filed Feb. 15, 2006, thecontents of all of which are incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to a method and apparatus for providing adistributed synchronization and timing system, of particular, but by nomeans exclusive, use in providing clocks, data acquisition and controlof test and measurement equipment, instrumentation interfaces andprocess control equipment, synchronized to an essentially arbitrarydegree.

BACKGROUND OF THE INVENTION

The USB specification is intended to facilitate the interoperation ofdevices from different vendors in an open architecture. USB data isencoded using differential signalling (viz. two wires transfer theinformation) in the form of the difference between the signal levels ofthose two wires. The USB specification is intended as an enhancement tothe PC architecture, spanning portable, desktop and home environments.

The USB specification assumes that devices differ. This is true for theintended environments in which devices from a multiplicity ofmanufacturers are connected, but there exist other environments (such ascertain common industrial or laboratory environments) that require aspecification for operating multiple devices of a similar nature in asynchronized manner. The specification does not sufficiently addressthis issue. Such environments are typically those where testing,measuring or monitoring is performed, and which require the devices tobe synchronized to a more accurate degree than is specified. The USBspecification allows limited inter-device synchronization by providing a1 kHz clock signal to all devices. However, many laboratory andindustrial environments require synchronization at megahertz frequenciesand higher.

USB employs a tiered star topology, where hubs provide attachment pointsfor USB devices. The USB host controller which is located on the user'spersonal computer (PC), laptop or personal digital assistant (PDA)contains the root hub, which is the origin of all USB ports in thesystem. The root hub provides a number of USB ports to which USBfunctional devices or additional hubs may be attached.

In turn, one can attach more hubs (such as USB composite device) to anyof these ports, which then provide additional attachment points viaports for further USB devices. In this way, USB allows a maximum of 127devices (including hubs) to be connected, with the restriction that anydevice may be at most 5 levels deep.

The root hub in the host transmits a Start of Frame (SOF) signal packetevery 1 ms to every device, the time between two SOF packets beingtermed a frame. Each module receives this SOF packet at a differenttime, allowing for electrical delays inherent in USB topology. Thetopology implies that there may be a significant time delay (specifiedas ≦380 ns) for receiving the same signal between a device that isconnected directly to the host controller and a device, which is 5levels down. This is a severe restriction when there is a need tosynchronize devices at megahertz levels and above. Furthermore the USBspecification allows the host controller to fail to transmit up to fiveconsecutive SOF tokens.

Current synchronization between a USB host and a USB device is possibleby two types of USB transfers, Interrupt and Isochronous. Interrupttransfers allow guaranteed polling frequencies of devices with minimumperiods of 125 μs, whereas isochronous transfers guarantee a constanttransfer rate. Both methods require there to be traffic between thedevice and host for synchronization to take place and therefore reservemore bandwidth for higher degrees of synchronization. This unfortunatelymeans that the available USB bandwidth can be used up before the maximumnumber of devices has been connected. This approach also places on thehost the great computational burden of keeping 127 devices synchronizedto the host by means of software, yet still fails to address maintainingsynchrony between the devices as to the host the individual devicesrepresent separate processes.

Devices that contain a physical transducer of some kind, such as a laserdiode or a photodetector, may require clock and trigger information.Such devices, such as a laser diode with a modulated light output at 1MHz, may use a clock signal to perform transducer functions at regularintervals or at a constant frequency. A trigger signal is usually usedto start or end an operation at a set time. In the laser diode example,a trigger signal could be used to turn the modulated light output on oroff.

These clock and trigger signals or information (referred to below assynchronization information) can be used to synchronize a multiplicityof devices to each other, provided the signals are common andsimultaneous to all devices. ‘Common’ and ‘simultaneously’ here meanthat the variation in time of these signals between the devices is lessthan a specified quantity, δt. In the laser diode example, this wouldenable a multiplicity of laser diodes to modulate their light output atone frequency. The modulation frequency of all devices would be thesame, and their waveforms would be in-phase. The current USBspecification (viz. 2.0) allows for delays in δt of up to 0.35 μs. For asignal with a frequency of 1 MHz and a period of 1.0 μs, this delayrepresents almost half of the period. It is thus unusable as specifiedas a synchronization signal for routine use.

Devices like hubs and USB controller chips commonly use some amount ofphase locking in order to decode the USB protocol. It is the purpose ofthe SYNC pattern in the USB protocol to provide a synchronizationpattern for another electronic circuit to lock to. However, this isintended to synchronize the device to the USB bit streams to an accuracysufficient to interpret MHz bit streams. It is not intended tosynchronize two separate devices with each other to an accuracy requiredby many test and measurement instruments. The USB specification—to theextent that it deals with inter-device synchronization—is mainlyconcerned with synchronizing a USB-CD audio stream sufficiently foroutput on a USB-speaker pair. The requirements of such an arrangementare in the kHz range and, for this, the USB provides ideal conditions.However, the specification does not address the potential problems ofsynchronizing 100 USB-speaker pairs.

As discussed above, USB communication transfers data during regular 1 msframes or—in the case of the High-Speed USB specification—in eightmicro-frames per 1 ms frame. A Start of Frame (SOF) packet istransmitted to all but Low-Speed devices at the beginning of each frameand to all High-Speed devices at the beginning of each micro-frame. TheSOF packet therefore represents a periodic low resolution signalbroadcast to all but Low-Speed devices connected to a given HostController.

This SOF packet broadcast occurs at a nominal frequency of 1 kHz.However, the USB specification allows a very large frequency tolerance(by instrumentation standards) of some 500 ppm (parts per million). Thebackground art utilizes this low resolution frequency signal that isbroadcast to each of the devices to provide clock synchronization, butonly to the somewhat ambiguous frequency provided by the USB HostController.

U.S. Pat. No. 6,343,364 (Leydier et al.) discloses an example offrequency locking to USB traffic, which is directed toward a smart cardreader. This patent teaches a local, free-running clock that is comparedto USB SYNC and packet ID streams; its period is updated to match thisfrequency, resulting in a local clock with a nominal frequency of 1.5MHz. This provides a degree of synchronization sufficient to read thesmart card information into the host PC. As this approach is directed toa smart card reader, inter-device synchronization is not addressed.Further, neither a frequency lock to 1 kHz or better stability nor highaccurate phase control is disclosed.

U.S. Pat. No. 6,012,115 and subsequent continuation U.S. Pat. No.6,226,701 (Chambers et al.) addresses the USB SOF periodicity andnumbering for timing. As explained in the abstracts of thesedisclosures, the invention allows a computer system to perform anaccurate determination of the moment in time a predetermined eventoccurred within a real-time peripheral device by using the start offrame pulse transmitted from a USB host controller to peripheral devicesconnected to it.

However, these approaches do not measure the frequency of a periodicdata structure contained within the USB data traffic for determinationof the absolute frequency of the master clock in the USB Host Controllerand in some cases rely on the provision of an additional counter in thehost.

U.S. Pat. No. 6,092,210 (Larky et al.) discloses a method for connectingtwo USB hosts for the purpose of data transfer, by employing aUSB-to-USB connecting device for synchronizing local device clocks tothe data streams of both USB hosts. Phase locked loops are used tosynchronize local clocks and over-sampling is used to ensure that dataloss does not occur. This document, however, relates to thesynchronization of the data streams of two USB hosts with each other(and with limited accuracy) such that transfer of information is thenpossible between said Hosts. The invention does not teach about thesynchronization of a multiplicity of USB devices to a single USB Host orto a plurality of USB hosts.

The USB specification was written with audio applications in mind, andU.S. Pat. No. 5,761,537 (Sturges et al.) describes how to synchronizetwo or more pairs of speakers with individual clocks, where one pairoperates off a stereo audio circuit in the PC and the other pair iscontrolled by the USB. Since both speaker pairs use their own clocks,they need to be synchronized so this document teaches one technique formaintaining synchronization of the audio signals despite possible clockskew between the asynchronous clocks.

U.S. patent application Ser. No. 10/620,769 discloses a synchronizedversion of the USB, in which the local clock of each device issynchronized on a given USB to an arbitrary degree. This document alsodiscloses a method and apparatus for providing a trigger signal to eachdevice within the USB such that an event may be synchronously initiatedon multiple devices by the trigger signal.

U.S. Pat. No. 6,904,489 (Zarns) discloses methods and systems forremotely accessing a USB device, in which a requesting device (such as apersonal computer) issues a request for a USB device, the request isintercepted and packaged and then transmitted over a network. The packetis received by a USB host device, and the request is unpackaged andpassed to the controller for processing by the USB device.

FIG. 1 is a schematic diagram of an exemplary background artsynchronized USB device 10, connected to a digital USB 12, a clocksignal and synchronization bus 14, and including a digitally controlledtransducer 16. The device 10 also includes a bus connector 18, digitalI/O bus interface circuitry 20, a microprocessor 22, and synchronizationchannel 24 for passing synchronization information including trigger andclock signals to the transducer 16.

The device 10 is connected by means of the bus connector 18 to a digitalUSB 12 containing USB data and control signals for the USB device 10;clock signal and synchronization bus 14 provides clock andsynchronization signals.

Another synchronized USB device, disclosed in U.S. patent applicationSer. No. 10/620,769, is shown schematically at 10′ in FIG. 2. Likereference numerals have been used to refer to like features in FIG. 1.In device 10′, clock signals are generated locally to the synchronizedUSB device 10′ by decoding information present in the data stream of USB12, through bus connector 18. In this device, all synchronization isprovided through USB 12 using standard USB cables and connectors(rendering the clock signal and synchronization bus 14 of FIG. 1unnecessary). Synchronization channel 26 provides synchronizationinformation including trigger and clock signals to digital transducer16.

This architecture for synchronization of the local clock on each of aplurality of USB devices relies on periodic data structures present inthe USB traffic. The preferred embodiment of U.S. patent applicationSer. No. 10/620,769 essentially locks the local clock in frequency andphase to the detection of a SOF packet token at the USB device.

FIG. 3 is a schematic representation of another embodiment of U.S.patent application Ser. No. 10/620,769. In this embodiment, asynchronization channel 26 operates by detecting and extractinginformation from a USB 12 as USB signal traffic passes through todigital I/O bus interface circuitry 20 (not shown in this figure), andby generating both a local clock signal 28 and a local trigger signal30.

This embodiment employs circuitry to observe traffic through the USB anddecode all SOF packets, which results in a pulse once every 1 ms. Thelocal clock signal 28, from a controlled oscillator clock 32, is lockedto the reception of the USB 1 kHz SOF packet in both phase andfrequency.

This first requires the local high speed clock signal 28 from clock23—which may be, say, 1 MHz—to be divided by a clock frequency divider34 down to the frequency of the SOF packet reception (nominally at 1kHz). Matched filter 36 sends a clock synch signal 38 when a SOF packetarrives, which passes to a phase detector 40. The phase detector 40 iscoupled to the controlled oscillator clock 32 via a filter 42.

The local clock signal 28 is subsequently supplied to the transducercircuitry on the USB device (i.e. digital transducer 16 in FIGS. 1 and2), thus ensuring that all devices attached to the root hub are lockedin frequency to the point at which they receive the SOF packet token.

This arrangement is said to be able to produce a local clock signal toarbitrarily high frequencies, such as a clock frequency of tens ofmegahertz, and thereby to ensure that the local clock of each deviceconnected to a given USB is synchronized in frequency. U.S. patentapplication Ser. No. 10/620,769 also teaches a method and apparatus tofurther synchronize multiple local clocks in phase by measurement ofsignal propagation time from the host to each device and provision ofclock phase compensation on each of the USB devices.

However, the approach described in U.S. patent application Ser. No.10/620,769 is limited in its ability to provide a precisely known clockfrequency to each device. The arrangement described above by referenceto FIG. 3 locks the frequency of each local clock to the reception ofthe SOF packet token. The rate of SOF packet generation is driven by thelocal crystal oscillator on a host PC. This is generally inaccurate andthe USB specification has a very large tolerance on clock frequency andsubsequent SOF rate. The USB specification dictates that the hostcontroller must send a SOF packet at a rate of 12 MHz ±500 ppm (partsper million), that is, 12 MHz ±0.05%.

This is a very large tolerance for clocks. For example, a standardcrystal oscillator has a central frequency tolerance of approximately 20ppm with temperature stability of approximately ±50 ppm across theusable temperature range. Even this tolerance is unacceptable for highlyaccurate clock systems. Time critical systems often require temperaturestabilized crystal oscillators with centre frequency tolerance andtemperature stability of approximately 5 ppm or better.

U.S. patent application Ser. No. 10/620,769 also teaches a method ofcontrolling the synchronized USB clock frequency by manufacture of aspecial USB host controller with local clock of precisely controlledreference frequency. Such a system would then produce a USB data streamwith 1 kHz SOF clock accuracy of a few parts per million. This device islikely to be too costly to see widespread implementation in the highlycompetitive personal computer market; further, systems such as laptopcomputers and PDAs (personal digital assistants) have no provision toadd on an aftermarket USB host controller.

U.S. Pat. No. 6,226,701 (Chambers et al.) discloses a system fortime-stamping real-time events within a USB, employing multiple countersand comparing elapsed time since USB SOF packets. This system requires acounter in both the USB device and the USB Host Controller to beactivated by SOF tokens. The counter in the device is activated by theexternal event and stopped by the next SOF. The counter in the Hostcontroller is reset and started by each SOF. The USB host controllerinterrogates the peripheral device which transfers data to the hostcontroller indicating (i) that an event has occurred, and (ii) the timebefore start of frame value of the first timer. The USB host controllerinterrupts the host processor and transfers to it the data related tothe peripheral device. In this way the system of this document candetermine the elapsed time since the external event occurred and theprocessor read the second timer.

However, while the system of Chambers et al. can perform basic eventtime-stamping, it requires a specific hardware implementation of the USBHost Controller and is therefore not compatible with a genericimplementation of USB. Furthermore, that system relies on PC interruptfeatures and the associated timing restrictions of the real-time clockof the Host PC.

SUMMARY OF THE INVENTION

Thus, it is an object of this invention to supplement the USBspecification such that any number of USB devices, up to some allowedmaximum, can operate in a synchronized and triggered manner with localclocks both phase and frequency locked to precisely controlled arbitraryfrequencies.

It is another object of the invention to retain the advantages of USBwhile supplementing the USB specification, including the ability tooperate multiple devices via a tiered star architecture (up to a currenttotal of 127 devices), hot-swap capability, automatic enumeration,ease-of-use, cross-operating system compatibility, and portability.

It is yet another object of this invention to provide highly accuratetime-stamping of the events of a real-time system with genericimplementation of USB Host controller hardware applicable to every USB.

In a first broad aspect, the invention provides a method and apparatusfor controlling the phase and frequency of the local clock of a USBdevice, the apparatus comprising:

-   -   circuitry for observing USB traffic and decoding from the USB        traffic a periodic data structure containing information about        frequency and phase of a distributed clock frequency and phase;        and    -   circuitry for receiving the periodic data structure and        generating from at least the periodic data structure a local        clock signal locked in both frequency and phase to the periodic        data structure.

Thus, the periodic structure acts as a carrier for clock information,without itself constituting the clock frequency information. The clockmay either be of the same frequency as the carrier or a differentfrequency according to any number of additional signals used to modifythe carrier signal frequency.

Indeed, the local clock signal can be generated with a frequency that isa non-integral multiple (including sub-multiple) of that of the periodicstructure/carrier signal; this is also the case in other aspects of theinvention described below. That is, the local clock signal need not begenerated with a frequency that is a fixed multiple of the frequency ofthe periodic structure/carrier signal, but rather with a frequency thatis calculated based on the actual frequency of the periodicstructure/carrier signal. For example, if the frequency of the periodicstructure/carrier signa is 1.01 kHz, according to the present inventionit is possible to synchronize to substantially exactly 10 MHz (ratherthan to an integral multiple, such as 10.1 MHz).

The circuitry for receiving the periodic data structure and generating alocal clock signal may also be adapted to receive an information signal(such as from a microcontroller) and to generate the local clock signalfrom at least the periodic data structure and the information signal.

The circuitry for receiving the periodic data structure and generating alocal clock signal may include a phase comparator, a controlledoscillator clock generator and frequency synthesis circuitry forgenerating a clock signal of arbitrary frequency.

The periodic data structure may comprise a USB Start of Frame (SOF)packet token.

According to a second broad aspect, the invention further provides amethod for generating a local clock signal, comprising:

-   -   measuring a frequency of a periodic data structure (such as the        SOF packet token) in a USB data stream.

In one embodiment, the method further comprises determining a clock rateof a USB host controller from the frequency of the periodic datastructure.

According to this broad aspect, the invention also provides an apparatusfor generating a local clock signal, comprising:

-   -   a USB adapted to receive a USB data stream;    -   a reference signal source for providing a reference signal; and    -   timing circuitry for comparing a periodic data structure in the        USB data stream (such as the SOF packet tokens) with the        reference signal and determining the frequency of the periodic        data structure.

Thus, in this aspect the frequency of the periodic data structure can bedetermined, which may itself be used to determine, for example, theclock rate of a USB host controller.

The USB may receive the USB data stream wirelessly, or the apparatus mayinclude a USB bus connector for connection to the USB and fortransmitting the USB data stream to the USB.

The apparatus will commonly be in the form of a USB device, but need notbe.

The apparatus may be adapted to measure the frequency of the periodicdata structure in only one of a plurality of devices and be configuredto transmit a signal to other devices to control their local clocksaccordingly.

The reference signal or frequency source (in this and other embodiments)may comprise either a local reference clock or an external referencesignal source (such as a connector for connection to an externalreference clock). If an external reference clock is employed in thisregard, it may be of arbitrarily high accuracy, and could be in the formof, for example, a precision frequency reference (such as a Caesium orRubidium clock), a Global Positioning System (GPS) time server or anIEEE-1588 time server.

The apparatus may include a time-stamp latch and a reference time-stampsignal source, wherein the time-stamp latch is adapted to time stamp adata signal from the reference time-stamp signal source, whereby thetime-stamp information can be synchronized to the reception of thecarrier signal.

The reference time-stamp signal source may comprise a connector forconnection to an external reference time-stamp signal source.

In a third broad aspect, the invention provides an apparatus fordetermining the clock rate of a USB host controller, comprising:

-   -   a USB hub attachable to the USB host controller;    -   a reference signal source for providing a reference signal;    -   a USB device attached to the USB hub and having timing circuitry        for comparing a periodic data structure in the USB data stream        with the reference signal and determining the frequency of the        periodic data structure so that an estimate of the clock rate        can be made.

Preferably, the apparatus comprises a plurality of USB devices attachedto the USB hub, each having timing circuitry for comparing a periodicdata structure in the USB data stream with the reference signal anddetermining the frequency of the periodic data structure, and theapparatus is operable to make respective estimates of the clock rate,wherein the apparatus further comprises a data processor for receivingthe respective estimates of the clock rate and for determining the clockrate of the USB host controller from (such as by statistical analysisof) the estimates.

The apparatus may make the estimates of the clock rate in the timingcircuitry of the respective USB devices, or in the data processor, orotherwise.

The reference signal source may be of arbitrarily high accuracy, andcould be in the form of, for example, a common Global Positioning System(GPS) time server or of a respective GPS time server corresponding toeach USB device.

Thus, a GPS time server can provide a reference clock signal to anarbitrary precision and phase accuracy to an arbitrary precision acrossthe earth, but any other reference clock signal (preferably externallyprovided) is suitable. It should also be understood that any externaldistributed reference timing system (such as the synchronous Ethernetstandard known as IEEE-1588) may also be used as the clocking referencesource for ensuring a widely distributed synchronous USB system.

In a fourth broad aspect, the invention provides a synchronized USB forsynchronizing a plurality of USB devices, comprising:

-   -   an external reference clock signal provided to the plurality of        USB devices enabling them to each synchronize themselves to the        external reference clock signal (and by implication to one        another).

Thus, according to this aspect, an essentially unlimited number of USBdevices can be synchronized, so that the synchronous channel count of asynchronized USB can be increased beyond the present limit of 127devices (including hubs) imposed by the USB specification. This enablesthe USBs to each synchronize themselves to that external referencesignal.

According to this aspect of the invention, there is provided a method ofsynchronizing a plurality of USB devices, comprising:

-   -   providing an external reference clock signal to the plurality of        USB devices; and    -   the USB devices synchronizing themselves to the external        reference clock signal (and by implication to one another).

The method may include synchronizing events on a plurality ofsynchronized USBs. Preferably, the method includes communicatinginformation to a further plurality of USB devices on said USB devicessuch that said further USB devices are triggered to execute commands orfunctions in real-time and as required by an operator.

Thus, according to this method, to extend the number of devices and thephysical separation of devices that USB can support in a synchronizedsystem can be extended. USB can currently support 127 devices (includinghubs) and with few exceptions is limited to a range of 30 m. In thisaspect a GPS or IEEE-1588 signal (for example) can be used as the localtiming reference for a plurality of USBs, so an essentially unlimitednumber of devices may be included in the system with no restriction ontheir locations. Hence, a globally synchronized system may be provided.

In a fifth broad aspect, the invention provides a method for reducingcommunication latency of a USB (such as for time critical applications,including control applications), comprising:

-   -   monitoring and decoding upstream USB data traffic associated        with the USB;    -   extracting specific information packets from said upstream        information; and    -   initiating at least one action according to content of the        specific information packets.

The specific information packets may be processed by a local processorbefore being acted upon.

In one embodiment, the action includes communicating with one or moreother devices (that is, outside the USB environment). This communicationmay include transmitting data to the other devices. The data may becommunicated through any communication channel, including a serialcommunication channel, a parallel communication channel, a wiredcommunication channel, a fiber optic communication channel, and awireless communication channel.

This aspect also provides a USB with reduced latency, comprising:

-   -   a USB device with an upstream port; and    -   a data decoder and processor for observing USB data traffic on        the upstream port, decoding data structures present in the USB        traffic, and initiating at least one action according to content        of the data structures.

Thus, according to this aspect, a new class of USB control device ispossible whereby the usual limitations of latency on the USB arereduced.

In a sixth broad aspect, the invention provides a synchronizedmultichannel USB synchronizable to a synchronized Ethernet, comprising:

-   -   a USB host system;    -   a synchronized multichannel USB;

a plurality of USB devices coupled to the USB host system, each having alocal clock and an absolute time register;

-   -   wherein the local clocks of the USB devices are synchronized in        frequency and phase, the absolute time registers of the USB        devices are synchronized and clocked by the respective local        clock, and the USB includes a synchronization channel whereby        clock frequency and time stamp information can be communicated        between the synchronized USB and the synchronized Ethernet and a        data channel for data communication with the synchronized        Ethernet.

The synchronization channel may comprise one or more USB devicesattached to the synchronized USB, a compound USB Hub and USB devicefunction, or a device that observes USB data traffic on the synchronizedUSB but is not an attached member of the synchronized USB.

In another broad aspect, the present invention provides a USB device,comprising at least one (and in some embodiments more than one) localclock, wherein the local clock is synchronized to the USB, whereby thelocal clock can be controlled to an arbitrarily precise frequency andphase.

The USB device may include a synchronizer for synchronizing the localclock with a carrier signal contained within a USB data stream, whereinaccuracy of a local clock frequency and phase is not limited by anaccuracy of a USB Host Controller clock. In this (and otherembodiments), the carrier signal may comprise USB data OUT tokens, INtokens, ACK tokens, NAK tokens, STALL tokens, PRE tokens, SOF tokens,DATA0 tokens, DATA1 tokens or programmable bit pattern sequences in theUSB data packets.

It should be noted that the various features of each of the aboveaspects of the invention can be combined as desired.

In addition, apparatuses according to the invention can be embodied invarious ways. For example, such devices could be constructed in the formof multiple components on a printed circuit or printed wiring board, ona ceramic substrate or at the semiconductor level, that is, as a singlesilicon (or other semiconductor material) chip.

BRIEF DESCRIPTION OF THE DRAWING

In order that the present invention may be more clearly ascertained,embodiments will now be described, by way of example, with reference tothe accompanying drawing, in which:

FIG. 1 is a schematic diagram of a background art synchronized USBdevice;

FIG. 2 is a schematic diagram of another background art synchronized USBdevice;

FIG. 3 is a schematic diagram of the details of background artsynchronized USB circuits;

FIG. 4 is a schematic diagram of a synchronized USB device according toa first embodiment of the present invention;

FIG. 5 is a schematic diagram of the synchronization channel of thesynchronized USB device of FIG. 4;

FIG. 6 is a is a schematic diagram of a device for synchronizing a USBaccording to a second embodiment of the present invention;.

FIG. 7 is a schematic diagram of the timing measurement circuitry of theUSB synchronizing device of FIG. 6;

FIG. 8 is a schematic diagram of a USB system according to a thirdembodiment of the present invention;

FIG. 9 is a schematic diagram of a USB system according to a fourthembodiment of the present invention;

FIG. 10 is a schematic view of a USB Timing Hub according to a fifthembodiment of the present invention;

FIG. 11 is a schematic view of a system for increasing the synchronouschannel count of a USB according to a sixth embodiment of the presentinvention;

FIG. 12 is a schematic diagram of a synchronized USB according to aseventh embodiment of the present invention;

FIG. 13 is a schematic view of a globally synchronized USB according tothe embodiment of FIG. 12;

FIG. 14 is a schematic diagram of a USB synchronized to an Ethernetaccording to a eighth embodiment of the present invention.

FIG. 15 is a schematic diagram of the USB-Ethernet synchronizingcircuitry of the USB Timing Hub of the USB of FIG. 14;

FIG. 16 is a schematic diagram of a hybrid USB hub according to a ninthembodiment of the present invention that provides a control path that isnot subject to the normal USB latency delays;

FIG. 17 is a schematic diagram of the USB monitoring circuitry of theHybrid USB Hub of the synchronized USB of FIG. 16;

FIGS. 18A, 18B and 18C schematically illustrate the data insertionswitch and method used in the USB monitoring circuitry of FIG. 17 toinsert payload data into a USB data stream;

FIG. 19 is a schematic diagram of a USB with Hybrid USB Host Controllersynchronized to an Ethernet according to a tenth embodiment of thepresent invention;

FIG. 20 is a schematic diagram of the Hybrid USB Host Controller of theUSB of the embodiment of FIG. 19;

FIG. 21 is a schematic diagram of a USB device with a notion of realtime according to an eleventh embodiment of the present invention;

FIG. 22 is a schematic diagram of the real time clock circuitry of theUSB device of FIG. 21;

FIG. 23 is a timing diagram of the USB device of FIG. 21; and

FIG. 24 is a schematic diagram of a USB device according to a twelfthembodiment of the present invention that can accurately time stampexternal events.

DETAILED DESCRIPTION OF THE INVENTION

A USB device according to a first embodiment of the present invention isshown schematically at 50 in FIG. 4, with a USB 52. In this embodiment,clock synchronization information to allow the local clock of the USBdevice 50 to be frequency controlled to an arbitrary degree is passed tothe USB device by a carrier signal (described below) that is thendecoded from the USB data stream.

Referring to FIG. 4, USB device 50 includes a bus connector 54, digitalI/O bus interface circuitry 56, a microcontroller 58, a digitallycontrolled transducer 60 and synchronization circuitry in the form ofsynchronizer 62 (described in greater detail below). The digital I/O businterface circuitry 56 acts as a transceiver for USB data detected atbus connector 54, passing the USB data to microcontroller 58. Themicrocontroller 58 provides information 64 to synchronizer 62 foraccurate frequency synthesis and a direct control channel 66 todigitally controlled transducer 60.

The carrier signal referred to above is a periodic data structure andhence usable as a carrier signal; in this and the other embodimentsdescribed below it is in the form of the SOF packet token, whichprovides a periodic low resolution signal of ambiguous frequency that isbroadcast to all but Low-Speed devices connected to a given HostController. The carrier signal, once decoded from the USB traffic, iscombined with a scaling factor to generate synchronization informationand hence to synthesize a local clock signal with precise control of theclock frequency.

Thus, FIG. 5 is a detailed schematic diagram of the synchronizer 62 ofthis embodiment. Synchronizer 62 includes a matched filter 68 to observeUSB traffic through bus connector 54, decode the aforementioned periodiccarrier signals (in the form, in this embodiment, of SOF packet tokens)and send a clock synchronization signal 70 to local clock synthesiscircuitry 72.

A frequency-accurate local clock signal 74 is synthesized from thedecoded carrier signal (i.e. clock synchronization signal 70), usinginformation signal 76 provided by microcontroller 58. In this embodiment(and typically) local clock signal 74 has a frequency several orders ofmagnitude higher than has clock synchronization signal 70 and is divideddown by a frequency divider 78 to a divided signal 80 of frequencycloser to that of clock synchronization signal 70.

Local clock synthesis circuitry 72 manipulates its input signals (i.e.clock synchronization signal 70 and divided signal 80) according toinformation signal 76 provided by microcontroller 58. The resulting twooutput signals 82 and 84 are passed to a phase comparator 86. The phasecomparator 86 is coupled via a filter 88 to a controlled oscillatorclock generator 90.

Accurate local clock signal 74 is then used as clock signal for triggercircuitry to generate a phase accurate trigger signal 92. Synchronizer62 includes a further matched filter 94 that also decodes USB datareceived through the USB bus connector 54 and produces a trigger enablesignal 96 upon detection of the required trigger signal from the USBdata stream. The trigger enable signal 96 is passed to a data latch 98,which uses the local frequency accurate clock signal 74 to clock thetrigger enable signal 96 through to form phase accurate trigger signal92.

According to this embodiment, therefore, it is possible to produce aclock signal stable to arbitrarily high frequencies, such as a clockfrequency of tens of megahertz with stochastic jitter as low as a fewnanoseconds or less, and with arbitrarily high frequency accuracy.

As discussed above, the SOF packet broadcast occurs at a nominalfrequency of 1 kHz but the actual frequency of this signal is determinedby the accuracy of the USB Host Controller clock. A USB device 100according to a second embodiment of the invention employs a method fordetermining the effective clock rate of the USB Host Controller byaccurately measuring the frequency of the SOF packet. This signal canthen be considered a carrier for information about the Host Controllerclock rate and the carrier signal is broadcast to all connected USBdevices. The carrier signal embedded in the normal USB protocol is thusdecoded and its frequency measured to determine the effective clock rateof the USB Host Controller clock.

Thus, FIG. 6 is a schematic diagram of a device 100 for synchronizing aUSB according to a second embodiment of the invention, which includes aUSB bus connector 102 for connection to a USB. Device 100 has a firstconnector 104 for receiving an external reference clock signal, and asecond connector 106 for receiving an external reference time-stampsignal, by mean of which device 100 measures the frequency of the SOFpacket signal (or carrier signal). Device 100 includes USB monitoringcircuitry 108 to observe the USB data stream, a microcontroller 110,timing measurement circuitry 112 and information bus 114 (incorporatingan analog and/or a digital bus) for communication betweenmicrocontroller 110 and timing measurement circuitry 112.

Although device 100 determines the SOF packet carrier signal frequencyand by implication the USB Host Controller frequency, and can passinformation about the frequency back to a microcontroller and indeedback to a host PC, it will be apparent to those skilled in the art thatthis approach may also be used with non-USB devices. For example, thisapproach may be used in a device that merely detects and decodes a USBdata stream but is not a USB device.

Although device 100 determines the SOF packet carrier signal frequency,it will be apparent to those skilled in the art that both the connectorfor receiving external reference clock signal 104 and the connector forreceiving external reference time-stamp signal 106 can be bidirectionalports. Such bidirectional ports can transmit or receive clock and datasignals (including time-stamp information) to or from an externaldevice. It will also be apparent to those skilled in the art that suchsignals can be used for controlling external devices.

FIG. 7 is a more detailed schematic diagram of the timing measurementcircuitry 112. Timing measurement circuitry 112 includes a matchedfilter 116 for decoding the carrier synchronization signal in the USBdata stream to output a decoded carrier signal 118, and frequencymeasurement circuitry 120 that compares decoded carrier signal 118 witha local reference signal 122. The frequency measurement circuitry 120produces clock accuracy information signal 124 indicative of theabsolute clock accuracy of the carrier signal and hence indicative ofthe clock rate of the USB Host Controller. (This clock accuracyinformation signal 124 is passed through information bus 114 of FIG. 6.)Local reference signal 122 is provided by multiplexer 126, which selectseither local reference clock signal 128, generated by local referenceclock 130, or an external reference signal 132 (provided by firstconnector 104), as controlled by microcontroller 110 through informationbus 114.

The decoded carrier signal 118 is also used by time-stamp latch 134,which time stamps a data signal 136 received from external time-stampsecond connector 106, and output at 138 to information bus 114. In thisway, absolute time-stamp information from an external source can besynchronized to the reception of the carrier signal.

FIG. 8 is a schematic diagram of a USB system 140 according to a thirdembodiment of the present invention, in which a personal computer 142with a USB Host Controller 144 is attached to a single USB device 146 ata USB 148. The USB device 144 contains timing measurement circuitry 150(as per timing measurement circuitry 112 of FIG. 7) to measurerepetitive carrier signal frequency using an internal reference clock(comparable to local reference clock 130 of FIG. 7) to an arbitrarydegree. Thus, in this embodiment the absolute frequency of the clockcarrier signal of the USB Host Controller 144 is determined by means ofcircuitry (i.e. the timing measurement circuitry 150) contained solelywithin a USB device. Further, it will be apparent to those skilled inthe art that, although this embodiment includes a personal computer,alternative similar embodiments may instead include any device, such asa personal digital assistant (PDA) or mobile communication device thatcontains a USB host controller or USB on-the-go controller.

FIG. 9 is a schematic diagram of a USB system 160 according to a fourthembodiment of the present invention, in which personal computer 162 witha USB Host Controller 164 is attached to a USB hub 166 at a USB 168. USBHub 168 provides connectivity to a plurality of USB devices 170, each ofwhich contains timing measurement circuitry (comparable to timingmeasurement circuitry 150 of USB system 140) to measure repetitivecarrier signal frequency using an internal reference clock (comparableto local reference clock 130 of FIG. 7). Each of the USB devices 170measures carrier signal frequency with some finite error. As the erroris essentially random, statistical analysis is used to analysemeasurements from the USB devices 170 and thereby reduce the overalluncertainty in measurement of the carrier signal frequency.

Thus, in this embodiment, the absolute frequency of the clock carriersignal frequency of USB Host Controller 164 is determined to a greateraccuracy than would be achievable with a single USB device.

FIG. 10 is a schematic representation of a USB Timing Hub 180 accordingto a fifth embodiment of the present invention. The USB Timing Hub 180has an upstream port 182 for connection to a Host Controller (orintermediate upstream device between USB Timing Hub 180 and a HostController), a plurality of downstream ports 184 (that provide USBexpansion), an external reference clock input port 186, and an externalreference time-stamp input port 188.

USB upstream port 182 is connected to USB Hub circuitry 190 thatprovides USB expansion to the plurality of downstream USB ports 184; oneof the downstream USB ports 184 is directed to an internal USB device192. Internal USB device 192 is connected to timing measurementcircuitry 194 (comparable to timing measurement circuitry 112 of FIG. 6)via a communication bus 196. The timing measurement circuitry 194contains an internal local reference clock (comparable to localreference clock 130 of FIG. 7) and also receives information from bothexternal reference clock input port 186 and external time-stamp inputport 188. The timing measurement circuitry 194 also observes USB datatraffic on the upstream port 182 with USB monitoring circuitry 198 anduses this signal 199 to decode the USB Host Controller clock carriersignal for measurement of the carrier signal frequency.

Thus, USB Timing Hub 180 contains both circuitry 194 (of the typedescribed by reference to FIG. 7) to determine the absolute clock rateof a USB Host Controller and normal USB Hub circuitry 190. Such a hybriddevice provides both USB Host Controller clock carrier signal frequencyinformation and expansion of the USB.

According to a sixth embodiment of the present invention, thesynchronous channel count of a USB system can be extended beyond thatallowed by the USB specification (which is currently 127 devicesincluding hubs). This embodiment allows a plurality of discrete USBs tobe synchronized by delivering a common external reference clock signalto each of the USBs. The common reference clock signal is then used tomeasure the USB Host Controller clock carrier signal of each of the USBsand subsequently to use that information to synthesize a known frequencyon the local clocks on each USB device connected to any of the USBs toan essentially arbitrary degree.

Thus, FIG. 11 is a schematic view of a system 200 according to a sixthembodiment for increasing the synchronous channel count of a USB, inwhich a plurality of synchronized USBs are synchronized to an arbitrarydegree. The system 200 includes a plurality of personal computers 202,each containing a USB Host Controller 204. Each personal computer 202 isconnected to a hybrid USB Timing Hub 206 (of the type described andillustrated at 180 to FIG. 10); each USB Timing Hub 206 provides aplurality of synchronized USBs 208 to allow expansion to a plurality ofUSB devices 210. An external reference clock 212 provides a signal tothe synchronized USBs 208 by means of the USB Timing Hubs 206. In analternative arrangement, system 200 omits the USB Timing Hubs 206, andthe USB devices are configured to receive the external reference clocksignal directly. However, the use of the USB Timing Hubs 206 arepreferred.

According to a seventh embodiment of the present invention, asynchronized USB is provided with an external reference clock signalthat is frequency accurate and time-stamp accurate to an arbitrarydegree. These signals allow the USB to be synchronized to an arbitraryaccuracy. This embodiment uses an external Global Positioning System(GPS) Time Server as the external synchronization reference. The GPSTime Server reference clock signal is delivered by means of satellitecommunication. Furthermore, the GPS Time Server can deliver absolutetime-stamp information accurate to an arbitrary degree, regardless ofposition, essentially anywhere.

Thus, FIG. 12 is a schematic diagram of a system 220 in which a USB 222is synchronized to a GPS Time Server 224. System 220 includes a personalcomputer 226 containing a USB Host Controller 228, connected tosynchronous USB 222, where synchronous clock frequency is accurate to anarbitrary degree.

USB port 230 of personal computer 226 connects to USB Timing Hub 232,which provides downstream expansion ports 234 for the attachment ofadditional USB devices 236. USB Timing Hub 232 (of the type describedand illustrated at 180 to FIG. 10) also has ports 238, 240 forreceiving, respectively, a reference clock signal 242 and time-stampinformation 244 from GPS Time Server 224. The GPS Timer Server 224 isconnected to an antenna 246 for receiving GPS time and positioninformation.

It will be appreciated that other means for providing a globallysynchronized external reference clock and time signal may be employed inthis embodiment, without departing from the scope of the invention.

FIG. 13 is accordingly a schematic representation of a USB 250 globallysynchronized according to this embodiment. Globally synchronized USB 250comprises a plurality of USBs located at different locations 252; eachis of the type shown at 222 in FIG. 12, so each is synchronized by aseparate GPS Time Server. The plurality of GPS Time Servers providereference clock signals that are frequency locked to an essentiallyarbitrary degree by means of satellite communication. Furthermore, theplurality of GPS Time Servers each deliver absolute time-stampinformation to their respective USB Timing Hub accurate to an arbitrarydegree, regardless of position, anywhere on earth.

Thus, a plurality of otherwise independent USBs are synchronized. Such asystem is capable of accurate synchronization anywhere on earth for awidely distributed synchronous USB. This also has the capability ofunlimited channel count by adding as many synchronized USBs (222 of FIG.12) as desired.

According to a eighth embodiment of the present invention, asynchronized USB can be synchronized to a synchronized Ethernet (thatis, a network that is in internal data communication according to theEthernet protocol). In this embodiment, the synchronized USB is providedwith an external signal from a synchronized Ethernet that containstiming information according to IEEE-1588 Precision Time Protocol. Saidexternal signal contains both an Ethernet communication pathway and aPrecision Time Protocol pathway. In this way, both data and timinginformation can be communicated between USB and Ethernet systems.

Thus, FIG. 14 is a schematic diagram 260 of a USB 262 synchronized toEthernet 264. The synchronized Ethernet 264 contains a plurality ofdevices 266 to be synchronized and an Ethernet Boundary Clock 268. TheBoundary Clock 268 performs Ethernet connectivity between devices aswell as compensating for latency and timing jitter present intraditional Ethernet switches and routers. The synchronized USB 262includes a personal computer 270 with a USB Host Controller 272 and,connected to Host Controller 272, a hybrid USB Timing Hub 274. USBTiming Hub 274 provides connectivity expansion to a plurality of USBdevices 276. USB Timing Hub 274 includes an IEEE-1588 compatible port278 for communication of data and timing information 280 to synchronousEthernet 264.

The IEEE-1588 Precision Time Protocol contains a protocol fordetermining which node of a network is the time-base master. It will beapparent to those skilled in the art that any node (viz. device 266) ofthe synchronous Ethernet 264 or the synchronous USB 262 can be thetime-base master clock depending on the absolute accuracy of all deviceclocks.

FIG. 15 is a detailed schematic diagram of USB Timing Hub 274 of USB 262of FIG. 14. The hybrid USB Timing Hub 274 has an upstream port 292 forconnection to Host Controller 272 (or an intermediate upstream devicebetween USB Timing Hub 274 and Host Controller 272), a plurality ofdownstream ports 294 (that provide USB expansion) and external port 278for connectivity to the synchronous Ethernet.

USB Timing Hub 274 includes USB Hub circuitry 298, to which USB upstreamport 292 is connected, that provides USB expansion to the plurality ofdownstream USB ports 294; one of the downstream USB ports 294 isdirected to an internal USB device 300. Internal USB device 300 isconnected to timing measurement circuitry 302 (comparable to timingmeasurement circuitry 112 of FIG. 6) via a communication bus 304.

Timing measurement circuitry 302 also observes USB data traffic on theupstream port 292 by means of USB monitoring circuitry 306, and uses thesignal 308 therefrom to decode the USB Host Controller clock carriersignal for measurement of the carrier signal frequency. Timingmeasurement circuitry 302 contains an internal local reference clock(comparable to local reference clock 130 of FIG. 7) and also receives ortransmits information to an additional local clock 310 through clockcontrol channel 312. In this way, either the local clock 310 or a clockin the form of timing measurement circuitry 302 can be the local masterclock for use determining the carrier signal frequency.

USB Timing Hub 274 includes a synchronous Ethernet controller 314 towhich is connected external port 278 and which provides externalEthernet connectivity and supports IEEE-1588 Precision Time Protocol.Synchronous Ethernet controller 314 has a data channel 316 forcommunication of data between the external Ethernet (shown at 264 inFIG. 14) and internal USB device 300. In this way data is transferredfrom the external synchronous Ethernet 264 via synchronous Ethernetcontroller 314 and internal USB device 300 the personal computer (270 ofFIG. 14).

Synchronous Ethernet controller 314 also contains a synchronizationchannel 318 through which local clock 310 can be synchronized toexternal Ethernet 264. In this way timing information is passed betweensynchronous Ethernet controller 314 and local clock 310, therebyeffecting a hybrid synchronized USB/Ethernet system using the best ofboth interfaces: Ethernet provides wide ranging connectivity but limitedsynchronization capabilities, while USB provides a local precisionsynchronization network.

According to a ninth embodiment of the present invention, a USB isprovided that provides a control path that is not subject to the normallatency delays of USB (such as the 30 ms time frame implied by thetypically 30 ms thread cycle time of the Windows (trade mark) operatingsystem). Thus, FIG. 16 is a schematic diagram of a hybrid USB hub 330according to this embodiment that provides an additional data pathwayfor reducing USB control loop latency. USB hub 330 has an upstream port332 for connection to a Host Controller (or intermediate upstream devicebetween Hybrid USB Hub 330 and a Host Controller), a plurality ofdownstream ports 334 (that provide USB expansion) and an externalcontrol port 336 for connectivity to external interfaces, equipment ortransducers.

USB hub 330 also has USB Hub circuitry 338 (connected to Upstream port332) that provides USB expansion to the plurality of downstream USBports 334, and an internal USB device 340 to which is directed one ofthe downstream USB ports 334. USB hub 330 includes an internal USBdevice 340 and a Data Decoder and Processor 342, mutually connected by acommunication bus 344.

Data Decoder and Processor 342 observes USB data traffic on the upstreamport 302 with USB monitoring circuitry 346 and uses the resulting signal348 to decode USB communications. Communication between Data Decoder andProcessor 342 and external control port 336 is controlled by anInterface 350. Interface 350 can be an Ethernet interface, a serialcommunication interface (such as a SPI (Serial Peripheral Interface)bus, a CAN Controller Area Network, a ProfiBus, a Process Field Bus or aUSB (including USB-on-the-go), a parallel communication interface (suchas a Centronics (trade mark) Parallel Port or an IDE (Integrated DriveElectronics) bus). Furthermore, external control port 336 can provideeither single-ended or differential signalling, and can be adapted toany desired form of connectivity, whether copper cabling, fibre-opticalcabling, wireless communication channels or otherwise.

In this way, data that is being transmitted between a Host Controllerand any USB device attached to downstream ports 334 can be interceptedand interpreted in USB hub 330 and used to immediately control anexternal device through the external control port 336. This circumventsthe normal communication and control loop latency of USB.

It will be apparent to those skilled in the art that, although variousembodiments of the present invention described herein include a hybridUSB Hub, these techniques need not be employed in a USB hub, but may infact be used in any device that is at least attached to a USB for thepurpose of detecting USB data flows and acting on the informationcontained therein.

Thus according to a variation of the ninth embodiment of the presentinvention, there is provided a system with a hybrid USB hub (comparableto USB hub 330 of FIG. 16) with an additional data pathway that allowscontrol loop responses to be reduced to an arbitrarily short time. FIG.17 is a schematic diagram of USB monitoring circuitry 360 (comparable toUSB monitoring circuitry 346 of USB hub 330 FIG. 16); USB monitoringcircuitry 360 has an upstream port 362 for connection to the HostController side of the bus, a downstream port 364 for connection to thedevice side of the bus, a USB data monitoring port 366 for transmissionof a replica of the USB data stream present at the USB upstream port362, a data switch control port 368 for controlling internal datapathways inside the circuit, a bidirectional data port 370 and bufferingcircuitry 372. Buffering circuitry 372 observes USB data signal 374(which comprises bidirectional communications between the HostController and attached devices) and provides a buffered replica signal376 thereof. Replica signal 376 is an exact copy of the bidirectionalcommunication present on the USB, is transmitted on the USB datamonitoring port 366 and is typically comparable to signal 308 of FIG.15.

Thus, USB monitoring circuitry 360 is able to monitor all USB datapackets and provide a buffered replica signal 376 of USB data signal 374for use by external circuitry. Buffered replica signal 376 can be usedby external circuitry for decoding periodic signal structures from theHost Controller within USB data to identify carrier signals whichcontain information about the clock rate of the USB Host Controller.Buffered replica signal 376 can also be used to decode information fromall downstream USB devices as it passes upstream toward the HostController. In this way, direct action can be taken on the informationfrom downstream devices without first requiring the Host Controller andassociated operating system to process and act on the data.

USB monitoring circuitry 360 also includes additional circuitry foradvanced data management, switching and reducing USB control looplatency, including a USB data switch 378 (shown as a pair of simplesingle pole switches in FIG. 17 for simplicity, though in reality USBdata signals are differential) and data controller circuitry 380 forcontrolling USB data switch 378. USB data switch 378 contains anupstream switch 382 and a downstream switch 384, and is configured tosynchronously direct USB data signal 374 from upstream port 362 eitherdirectly to the downstream port 364 (the configuration shown in FIG. 17)or utilising a bidirectional data stream 386 from external circuitry viabidirectional data port 370. USB data switch 378 has access to bufferedreplica signal 376, and data controller circuitry 380 is configured bydata switch control port 368. In this way, USB data switch 378 can beswitched synchronously with the USB data signal as monitored at 374.

USB monitoring circuitry 360 is also able to dynamically configureitself to insert data within a USB data stream. A message from the HostController to a device may be intercepted and altered by USB monitoringcircuitry. In this way, software can be configured to provide regularpolling of a particular USB device with a known data packet size. USBmonitoring circuitry, having access to the size of a specified regularlypolled packet, can insert data within the payload of a transaction bysynchronously bypassing the direct connection (viz. the configuration ofUSB data switch 378 shown in FIG. 17) and inserting data into thepayload field of the transaction.

FIG. 18A depicts the configuration of USB data switch 378 of FIG. 17 fordownstream insertion of payload data 388 at 378′; FIG. 18B depicts theconfiguration of USB data switch 378 of FIG. 17 for upstream insertionof payload data 390 at 378″. During downstream insertion of data theswitch must initially be configured as shown at 378 in FIG. 17 while thehost transmits the transaction packet header information, but switch toconfiguration 378′ of FIG. 18A for insertion of the payload and CRC data388. For upstream insertion of data, the device waits until it detectsthe polling request from the Host Controller before switching toconfiguration 378″ of FIG. 18B for transmission of the entire upstreamtransaction (including header). It should be noted that the device mayalternatively wait for the upstream transaction packet header passupstream before switching to configuration 378″ of FIG. 18B andinserting the payload data 390.

FIG. 18C is a schematic timing diagram for downstream data insertion(upper portion of the figure) and the upstream data insertion (lowerportion of the figure), indicating the configuration of the USB dataswitch.

According to a tenth embodiment of the present invention, there isprovided a Hybrid USB Host Controller that is synchronized to asynchronized Ethernet, to ensure that the attached synchronized USB isalso synchronized to the synchronized Ethernet. The Hybrid USB HostController is provided with an external signal from a synchronizedEthernet that contains timing information according to IEEE-1588Precision Time Protocol. The external signal contains both an Ethernetcommunication pathway and a Precision Time Protocol pathway. In thisway, both data and timing information can be communicated between HybridUSB Host Controller and Ethernet systems.

In this embodiment, the Hybrid USB Host Controller contains an embeddedmicrocontroller so that it is a stand-alone device that is not dependenton a host personal computer. The Hybrid USB Host Controller may containa standard USB Host controller, a USB-on-the-go Host Controller, awireless USB Host Controller or any other form of USB Host Controller.

FIG. 19 is a schematic diagram of a system 400 according to thisembodiment, comprising stand-alone USB 402 (that is, one containing anembedded controller that does not require attachment to a personalcomputer) and an Ethernet 404, synchronized to each other. The Ethernet404 typically contains an Ethernet Boundary Clock 406 and a plurality ofdevices to be synchronized 408. Boundary Clock 406 performs Ethernetconnectivity between devices as well as compensating for latency andtiming jitter present in traditional Ethernet switches and routers. USB402 consists of a Hybrid USB Host Controller 410 and a plurality of USBdevices (or USB Hubs for further expansion) 412.

In this embodiment, Hybrid USB Controller 410 contains an embedded USBHub functionality providing a plurality of downstream expansion ports.Hybrid USB Controller 410 also includes an IEEE-1588 compatible port 414for communication of data and timing information 416 to Ethernet 404.

FIG. 20 is a more detailed schematic diagram of Hybrid USB HostController 410 of FIG. 19. Hybrid USB Host Controller 470 has aplurality of downstream ports 472 (that provide USB expansion), anembedded controller 474, USB Hub circuitry 478 and USB master clockcircuitry 480. Controller 474 has an embedded microcontroller 482,external interface circuitry 484 and a USB Host Controller 486. USB HostController 486 is connected to USB Hub circuitry 478 that provides USBexpansion to the plurality of downstream USB ports 472 and USB masterclock circuitry 480 through a clock bus 488.

USB master clock circuitry 480 contains an internal local referenceclock 490 and also receives or transmits information to an additionallocal clock 492 (also a part of Hybrid USB Host Controller 410, and inthe form of a synchronous Ethernet IEEE-1588 clock) through a clockcontrol channel 494. Hybrid USB Host Controller 410 further includes asynchronous Ethernet controller 496, to which external port 414 isconnected and which provides external Ethernet connectivity and supportsIEEE-1588 Precision Time Protocol. Synchronous Ethernet controller 496has a data channel 498 for communication of data between the externalEthernet and external interface circuitry 484 of embedded controller474. A bidirectional data link is therefore provided between theexternal synchronous Ethernet and the synchronized USB throughsynchronous Ethernet controller 496 and the embedded controller 474.

Synchronous Ethernet controller 496 also has a clock control channel 500for communicating with synchronous Ethernet clock 492. IEEE-1588 clock492 may be either the bus master if it is more accurate than the clocksof other attached IEEE-1588 clocks or a slave clock that is slaved to amore accurate attached IEEE-1588 clock. Hybrid USB Host Controller 410includes a control channel 502 between external interface circuitry 484of embedded controller 474 and USB master clock circuitry 480 enablingthe embedded controller 474 to control clock signals. In a similar wayeither the local reference clock 490 or the IEEE-1588 clock 492 acts asthe system master clock, according to which is the more accurate.

USB Host Controller 486 uses the clock signal from clock bus 488 as itsmaster timing reference. This clock signal can be precisely tuned in USBmaster clock circuitry 480 to provide a frequency accurate timereference to arbitrary precision for synchronous USB control.Accordingly, the frequency of a periodic signal structure (such as aStart of Frame token) in the USB data stream can be accuratelycontrolled, resulting in a synchronized USB with precisely controlledtiming. In this way a hybrid synchronized USB/Ethernet system isachieved without requiring a personal computer. It will be apparent, inaddition, that latency can be improved in this arrangement according tothe approach described in the context of the embodiments of FIGS. 16 and17.

A USB device according to an eleventh embodiment of the presentinvention is shown schematically with a USB at 510 in FIG. 21. In thisembodiment, the synchronized USB device might be said to have somenotion of (or data indicative of) real time. This notion or data of timeis derived from USB bus transactions, the USB data stream andinformation received from the host system. Such a notion of real time isshared by all devices attached to the same USB.

Referring to FIG. 21, therefore, USB device 520 includes a bus connector522 for connecting to USB 524, digital I/O bus interface circuitry 526,a microcontroller 528, a digitally controlled transducer 530,synchronization circuitry in the form of synchronizer 532 (comparable tosynchronizer circuitry 62 of FIG. 5) and real time clock 534. Thedigital I/O bus interface circuitry 526 acts as a transceiver for USBdata detected at bus connector 524 and passes the USB data tomicrocontroller 528. The microcontroller 528 is provided with aninformation channel 536 to synchronizer 532 and a direct control channel538 to digitally controlled transducer 530.

USB device 520 has circuitry 540 at USB connector 522 that detects USBdata traffic on USB 524, and generates and passes a replica 542 of theUSB data traffic to synchronizer 532. Synchronizer 532 (which iscomparable to synchronizer 46 of FIG. 4) generates a local clock signal544 that is frequency and phase controlled to an arbitrary precision,and will be synchronous with those of any similar USB devices attachedto the same USB 524. Local clock signal 544 is passed to both thedigitally controlled transducer 530 to control its operation and to realtime clock 534.

Real time clock 534 can be synchronized to an absolute time and thenclocked by local clock signal 544. In this way, a plurality of USBdevices can operate sharing a common notion of real time each beingclocked by a synchronous local clock. Synchronization of the real timeclock 534 is initiated by a command from the host personal computer;this command is interpreted by microcontroller 528 and transferred toboth synchronizer 532 (via information channel 536) and real time clock534 through another information channel 546. Synchronizer 532 then actsto synchronize real time clock 534 through a real time synchronizingchannel 548. In this way, the real time clock can be synchronized to aknown time. Real time clock 534 can then deliver real time triggersignals 550 (which may also include a time stamp from the real timeclock) to control the operation of digitally controlled transducer 530such that it performs actions at specified time.

FIG. 22 is a detailed schematic diagram of the real time clock 534 ofUSB device 520 of this embodiment. Real time clock 534 has a controlport 558 for communication with microcontroller 528 (see FIG. 21), asynchronous clock input port 560 for receiving synchronous clock signals544 from synchronizer 532 (see FIG. 21), a synchronizing port 562 forreceiving synchronizing signals on synchronizing channel 546 (see FIG.21), an output port 564 and an input event/timestamp port 566.

Control port 558 receives information signals which are decoded byinterface 568 to provide a data signal 570 that contains the absolutetime value, which is loaded into a temporary register 572 (forsubsequent synchronous latching into real time clock counter 574), adata latch signal 576 for latching data signal 570 into the real timeclock counter 574, a counter enable signal 578 for enabling the realtime clock counter 574, and another data signal 580 to be loaded into acounter comparator 582.

Real time clock counter 574 also receives a synchronous clock signal 584from synchronous clock input port 560, which is used to increment thereal time clock counter 574, and a resynchronize signal 586 fromsynchronizing port 562, which can be used to synchronously clear thereal time clock counter 574. The resynchronize signal 586 is generatedfrom synchronizer 532 such that it occurs synchronously with a start offrame (SOF) token in the USB (or more precisely, synchronously with asynthetic SOF). This synchronizing synthetic SOF token frame number isknown to the host controller (which keeps track of rollover of thisnumber since the host began) and can therefore synchronize the device(or a plurality of similar devices) at the same point in time.Furthermore, the host maintains knowledge of the rollover of thissynthetic SOF token number and of the absolute timestamp of the realtime clock counter 574, so USB devices need not be synchronized at thesame point in time. Once a single USB device has been synchronized toreal time according to this technique, the host can calculate the realtime at any future synthetic SOF frame token. This allows any number ofdevices to be synchronized in a sequential manner.

In this way, real time clock counter 574 can either be synchronouslyloaded with a known ‘real time’ by microcontroller 528 (see FIG. 21) andtime counting initiated by resynchronizing signal 586, or synchronouslycleared by resynchronizing signal 586 with the counter incremented inboth cases by synchronous clock signal 584. The system controller (suchas a personal computer) then determines how the notion of time isrepresented by the real time clock counter 574.

The real time value 588 (a data signal) is clocked out of real timecounter 574 on each cycle of synchronous clock signal 584 to interface590 which provides signals for external circuitry through output port564. Furthermore, real time clock 534 can be configured to provide atrigger signal 592 by comparing the instantaneous real time value 588with a data signal that has previously been latched into countercomparator 582. Trigger signal 592 is then passed to output interface590 for transmission to external circuitry.

Interface 590 also receives external signals from an event withassociated timestamp data from external event/timestamp port 566. Thisdata 592 is passed to real time clock counter circuitry 574 forcalibration and setting of real time of the local clock containedtherein.

It should be noted that this notion of real time can be shared by aplurality of synchronized USBs, such as according to the approachemployed in system 220 of FIG. 12 or those embodiments described abovethat conform to IEEE-1588.

Furthermore, synchronous clock signal 584 and resynchronizing signal 586are synchronous with carrier signals (as described above in the contextof USB device 50 of FIG. 4). Thus, it is possible to determine the realtime of the reception of these carrier signals and hence set the realtime of real time clock counter 574 of FIG. 22.

FIG. 23 is a timing diagram 600 of the USB device 520 of FIG. 21.External event 602 of known real time can be used to start a localcounter 604, which is clocked from the synchronous clock signal 606(derived from synchronizer circuitry 62 of FIG. 4), and the real time608 of external event 602 is latched into the device. Reception of thenext decoded carrier signal 610 (synthetic start of frame) token stopslocal counter 604 and latches the number 612 of the frame token. Thehost controller can then determine the real time of latched frame tokennumber 612 using the time elapsed of local counter 604 (time At betweenthe event and the start of frame token).

In this way, an external event of known real time at event/timestampport 566 can be used to determine the real time of the arrival of localcarrier signal and hence set (or calibrate) the real time of a USBdevice 520. Real time determined by this method is latched into realtime clock counter (574 of FIG. 22) at 614. Such an externally derivedreal time event and time stamp may be generated by a known frequency andtime reference, such as a precision Caesium clock, a GPS time serverthat is locked to a global positioning satellite system or an IEEE-1588precision time protocol device.

In the absence of an external precision time stamped reference event602, the host personal computer can assign its own notion of time (fromits internal, inaccurate real time clock) to the synchronous USB. Thismethod merely assigns the personal computer's notion of time to a givencarrier frame number as the reference time for use by the real timeclock counter. From that time forward, the synchronous USB has highlyprecise relative accuracy (as defined by its real time clock countercircuitry) but with an offset from absolute time determined by theinitial error of the host personal computer's real time clock.

By extension, using multiple external events of known time, the carriersignal frequency can be determined to an arbitrary degree, using theapproach employed in device 100 of FIG. 6. This is a method ofgenerating a time stamp of an external event, relative to a knowncarrier signal number.

It should be noted that this approach can be implemented in a hub or aUSB device, or in a device attached to the USB. It can also beimplemented once or in multiple devices to improve accuracy bystatistical means.

A USB device according to a twelfth embodiment of the present inventionis shown schematically at 630 in FIG. 24. In this embodiment, thesynchronized USB device 630 can time stamp external events according toits own notion of time, which has either been calibrated by its own realtime clock or by an externally provided real time clock and time stamp.

The USB device 630 has an upstream port 632 for connection to a HostController (or intermediate upstream device between USB device 630 andsuch a host controller), an external trigger port 634 and a data port636 for communication of time stamp information. USB device 630 alsoincludes digital I/O bus interface circuitry 638, microcontroller 640and synchronizing time stamp circuitry 642. Time stamp circuitry 642includes synchronizing circuitry 646 (comparable to timing measurementcircuitry 302 of FIG. 15) that observes USB data traffic on the upstreamport 632 by means of USB monitoring circuitry 644 to synchronize a localclock using the carrier signal contained in decoded USB data streamsignal 650 and real time clock circuitry 648 (comparable to real timeclock 534 of FIG. 22).

External event signals (otherwise known as external triggers) connectedto external trigger port 634 and time stamp information present on dataport 636 are passed to time stamp circuitry 642 for processing. In thisway, external events (triggers) and associated time stamps can be passedto the device and correlated with a synchronized local clock containedin synchronizing circuitry 646.

Hence, once real time clock circuitry has been calibrated (such as bylatching real time into real time clock counter 574 of FIG. 22), allexternal events can be time stamped according to real time clock counter574.

Modifications within the scope of the invention may be readily effectedby those skilled in the art. It is to be understood, therefore, thatthis invention is not limited to the particular embodiments described byway of example hereinabove and that combinations of the variousembodiments described herein are readily apparent to those skilled inthe art.

In the preceding description of the invention, except where the contextrequires otherwise owing to express language or necessary implication,the words “Host Controller” may be used to specify a standard USB Hostcontroller, a USB-on-the-go Host Controller, a wireless USB HostController or any other form of USB Host Controller.

In the claims that follow and in the preceding description of theinvention, except where the context requires otherwise owing to expresslanguage or necessary implication, the word “comprise” or variationssuch as “comprises” or “comprising” is used in an inclusive sense, thatis, to specify the presence of the stated features but not to precludethe presence or addition of further features in various embodiments ofthe invention.

Further, any reference herein to prior art is not intended to imply thatsuch prior art forms or formed a part of the common general knowledge.

1-93. (canceled)
 94. A real-time synchronous multichannel USB system,comprising: a plurality of USB devices attached to a USB network, eachUSB device comprising a respective local clock, said respective localclocks of said USB devices being synchronized to each other; and eachUSB device further comprising a respective absolute time registercontaining a common notion of real time; wherein each respectiveabsolute time register is clocked by said respective synchronous localclock.
 95. A USB system as claimed in claim 94, adapted to providereal-time synchronization based on a signal received from a USB deviceattached to said USB network.
 96. A USB system as claimed in claim 95,adapted to provide real-time synchronization based on signals from acomposite USB hub and a USB device attached to said USB network.
 97. AUSB system as claimed in claim 94, adapted to provide real-timesynchronization based on a signal from an external device adapted toobserve USB traffic and provide information to a USB host systemcontroller of said USB network.
 98. A USB system as claimed in claim 94,wherein said absolute time registers are synchronized to a common notionof real time of a real-time clock of a host computing or other system.99. A USB system as claimed in claim 94, wherein said absolute timeregisters are synchronized to a common notion of real time of areal-time clock on one or more of said plurality of USB devices.
 100. AUSB system as claimed in claim 94, wherein said absolute time registersare synchronized to common notion of real time of an external timereference.
 101. A USB system as claimed in claim 100, wherein saidexternal time reference is adapted to synchronize to a globalpositioning system (GPS) satellite-based navigation and timing system,complies with IEEE-1588 precision time protocol across Ethernet, or isprovided by a time standard or protocol.
 102. A method of providing areal-time synchronous multichannel USB system, comprising: synchronizingrespective local clocks of each of a plurality of USB devices attachedto a USB network; providing a common notion of real time to respectiveabsolute time registers of each of said USB devices; and clocking saidabsolute time registers by the respective local clock.
 103. A method asclaimed in claim 102, including: setting said respective local absolutetime register of each of said USB devices to a predefined value at amoment of synchronization; and recording the real time of said moment ofsynchronization for each of said plurality of USB devices by a USBsystem controller.
 104. A method as claimed in claim 103, includingsynchronizing each of said USB devices substantially simultaneously.105. A method as claimed in claim 103, including synchronizing each ofsaid USB devices sequentially.
 106. A method of assigning a real time toa synchronized USB network, comprising: observing USB traffic;synchronizing a local clock of a synchronization device to carriersignals within said USB traffic; observing an external time event;latching a value of an external time-stamp that corresponds to saidexternal time event into a local register; initiating a local counter;monitoring a USB data stream local to said synchronization device forcarrier signals; generating a signal to stop said local counter onreceipt of a next carrier signal; detecting a frame number associatedwith said next carrier signal; and reporting a value of said localcounter, said frame number and said value of said time-stamp to a hostsystem; said host system assigning a real time to the synchronized USBnetwork for the frame number using the value of said local counter andthe value of said time-stamp.
 107. A method as claimed in claim 106,comprising determining a time of receipt of the carrier signal thatstopped said local counter;
 108. A method as claimed in claim 107,comprising: determining a period between receipt of said external timeevent and said numbered carrier signal.
 109. A method as claimed inclaim 108, including determining said period from a number of clockcycles of said local clock between receipt of said external time eventand of said numbered carrier signal and from the period of said localclock.
 110. A method as claimed in claim 106, including clocking saidlocal counter by said synchronized local clock or by an externalreference clock.
 111. A method as claimed in claim 106, wherein saidsynchronization device comprises a USB device or a composite USB hub andUSB device function.
 112. A method as claimed in claim 106, wherein saidsynchronization device is a non-USB device configured to observe USBdata traffic and pass information to a host system controller viaanother information channel.
 113. A USB device for generating anaccurate time-stamp of a real-time external event, comprising: a localclock synchronized to carrier signals within USB traffic; a real-timecounter register calibrated with a notion of real time, and clocked bysaid local clock; an event detector for detecting said real-timeexternal event; a data latch for latching a value of said real timecounter register on detection of said real-time external event; and adata link to a USB system controller for transmitting a time stampcorresponding to said value of said real time counter register ondetection of said real-time external event.
 114. A method of generatingan accurate time-stamp of a real-time external event in a synchronizedUSB network, comprising: synchronizing a local clock of a USB device;calibrating a real time counter with a notion of real time; clockingsaid real time counter using said local clock; detecting said real-timeexternal event; latching the value of said real time counter ondetection of said real-time external event and outputting acorresponding time-stamp; and transferring said time stamp to a USBsystem controller of said USB network.
 115. A synchronized USB systemadapted to generate an accurate time-stamp of a real-time externalevent, comprising: circuitry adapted to synchronize a local clock of aUSB device; circuitry adapted to calibrate a real time counter with anotion of real time; circuitry for clocking said real time counter usingsaid local clock; a detector for detecting said real-time externalevent; and a latch for latching the value of said real time counter ondetection of said real-time external event, outputting a correspondingtime stamp and directing said time stamp to a USB system controller ofsaid USB system.